It is known that non-volatile memory devices comprise a matrix of memory cells arranged in rows and columns. Reading of electrically erasable and programmable ROMs involves applying to the selected row, and thus to the gate electrode of the memory location or memory cell to be read, a voltage usually equal to the supply voltage of the memory device, and detecting the current flowing through the memory cell. In the case of a "written" cell, the threshold voltage thereof is approximately 5 V, or however higher than the voltage applied to its gate electrode; consequently, during reading no current flow is detected. In the case of an "erased" cell instead the threshold voltage thereof must be such as to guarantee the flow of current.
In order to have a proper operation and to assure reliability of the memory device in reading, it is necessary to pose limits to the memory cells' threshold voltage distribution; in particular, the distribution of the memory cells' threshold voltages must be comprised between approximately 0.5 V and 2.5 V. The lower limit is based on the simultaneous requirements of assuring that no "depleted" cells exist, i.e., cells having a threshold voltage lower than zero, and preventing damages to the thin limit stems from the intrinsic width of the distribution, generally a gaussian.
If the supply voltage is low, e.g., 2.5 V, all the erased memory cells with threshold voltages near the value of the supply voltage do not drain sufficient current, so that the reading thereof provides an incorrect result because the current flowing through the cell is too low and the cell is erroneously read as written.
Conventionally, this problem is solved by using boosting circuitries for the rows of the matrix, i.e., supplying the gate electrode of the cell to be read with a voltage higher than the supply voltage of the memory device. The boosted voltage is normally generated by means of a so-called "boost" capacitor that, after having been charged up to the supply voltage, is submitted at a first plate thereof to a voltage pulse equal to the supply voltage, so that at a second plate thereof a voltage higher than the supply voltage is obtained.
The voltage pulse is applied when it is necessary to access the memory cell.
The adoption of such a solution requires that the voltage boosting step starts together with the selection of the row, i.e., with the rise of the potential of the row to be accessed, corresponding to the node to be boosted, to values sufficiently near the supply voltage. To this purpose a dummy path is used simulating the real selection path of the row.
At the end of each read operation it is necessary to reset the initial conditions of the boosted nodes. In order to correctly carry out a successive access, it is in fact necessary that the nodes affected by boosting are at a correct voltage value, so that the desired boosted voltage value can be reached.
As mentioned, for a correct working of the boosting circuit the boost capacitor is charged up to the supply voltage of the memory device. For the principle of conservation of charge, when the plate of the capacitor which is at the lower potential is applied with the boosting pulse, the potential of the other plate is subjected to a corresponding increase of potential. The boosted voltage is the supply voltage of the driver circuits of the rows, so the boosted voltage is supplied to the row to be accessed and the information can be read by the sensing circuitry without the problems outlined above. Once the access to the memory cell has been performed, it is possible to come back to the rest conditions.
However, parasitic capacitances are connected to the plate of the boost capacitor which is boosted; thus, due to the presence of a capacitive partitioner formed by the boost capacitor and the parasitic capacitances, the charge stored in the boost capacitor is split between the boost capacitor and the parasitic capacitances, so that the voltage increase of the node to be boosted is lower than expected. When the initial conditions are re-established, i.e., when the voltage of the first plate of the boost capacitor is returned to ground, due to the charge conservation principle also the second plate of the boost capacitor undergoes the same voltage decrease. The boosted node thus takes a voltage value lower than that prior to the start of the boosting step (equal to the supply voltage), so that in order for that node to return to the initial value it is necessary to re-charge the boost capacitor. For boost capacitors of significant capacitances, typically 40-50 pF, the time required for the re-charge are approximately of 30-40 ns, unacceptable if compared to the average access times of non-volatile memories of about 100 ns.
The boost capacitor is normally re-charged by means of a P-channel transistor with source connected to the supply voltage; such a transistor operates with a small drain-to-source voltage difference, and thus it is not capable of furnishing high currents; even if a large transistor were employed, the recharge speed would not be significantly increased.
It is also clear that if a new read cycle were to start before the initial conditions on the boosted node are re-established, i.e., before the boost capacitor has been recharged, not only the voltage on the boosted node would not reach the desired voltage, but at the end of the boosting voltage pulse the voltage of the boosted node would be at an even lower value, until the voltage on the boosted node would no more be sufficient for assuring a correct reading.